TY  - BOOK
AU  - Ciletti,Michael D.
TI  - Modeling, synthesis, and rapid prototyping with the Verilog HDL
SN  - 0139773983
AV  - TK 7885.7 C572m 1999
U1  - 621.39/2 
PY  - 1999///
CY  - Upper Saddle River, N.J.
PB  - Prentice Hall
KW  - Verilog (Computer hardware description language)
KW  - Rapid prototyping
N1  - Includes bibliographical references and index
ER  -